The present invention relates to manufacturing high density, multi-metal layer semiconductor devices with a reliable interconnection pattern and, more particularly, to manufacturing high density multi-metal layer semiconductor devices with design features of 0.25 microns and under.
Escalating demands for high density and performance associated with ultra large scale integration require semiconductor devices with design features of 0.25 microns and under, e.g. 0.18 microns, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Conventional methodology for forming patterned metal layers employs a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region or gate electrode. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer, such as spin-on-glass (SOG) or high density plasma (HDP) oxide, is then applied to fill in the gaps, and the surface is planarized, for example, by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to match 0.25 micron design rules and below, such as 0.18 microns, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad for the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the bottom surface of the conductive via is in contact with the metal feature.
A conventional conductive via is illustrated in FIG. 1, wherein a first metal feature 100 of a first patterned metal layer is formed on first dielectric layer 110 and exposed by a through-hole 120 etched in second dielectric layer 130. The first metal feature 100, which has side surfaces that taper somewhat due to etching, typically has a composite structure comprising a lower metal layer 102, e.g., titanium (Ti) or tungsten (W), an intermediate or primary conductive layer 104, e.g., aluminum (Al) or an Al alloy, and an anti-reflective coating (ARC) 106, such as titanium nitride (TiN).
In accordance with conventional practices, the through-hole 120 is formed so that first metal feature 100 meets the bottom opening, thereby serving as a landing pad for the metal plug filling the through-hole 120 to form the conductive via 160. Thus, the bottom surface of the conductive via 160 is in contact with the first metal feature 100. The conductive via 160 electrically connects the first metal feature 100 and a second metal feature 140, which is part of a second patterned metal layer.
The second metal feature 140 is also typically a composite structure comprising a lower metal layer 142, a primary conductive layer 144, and an ARC 146. The plug filling the through-hole 120 to form the conductive via 160 is typically formed as a composite comprising a first adhesion promoting layer 150, which is typically a refractory material, such as TiN, Tixe2x80x94W, or Tixe2x80x94TiN, and a primary plug filling metal 170 such as W. Metal features 100 and 140 typically comprise metal lines with interwiring spacings therebetween conventionally filled with dielectric material 180, such as SOG or HDP oxide.
The anti-reflective coating 106 on the first metal feature 100 serves two purposes. First, it improves control over the definition of the photoresist mask through which the patterned metal layer was etched and, hence, the critical dimensions of the first metal feature 100. Fine control over the critical dimensions of the first metal feature are crucial for the ultimate conductance, resistance, and electromigration resistance of the metal line. For this purpose, it is desirable to for the thickness of the anti-reflective coating to be about 250 xc3x85-550 xc3x85.
Second, the anti-reflective coating 106 serves as an etch stop during the formation of the through-hole to prevent xe2x80x9cpunch through.xe2x80x9d Punch through occurs when the etching of the through-hole 120 cuts through the anti-reflective coating 106 and exposes the Al or Al-alloy primary conductive layer 104 of the first metal feature 100. Consequently, the Al therein may interact with the tungsten hexafluoride (WF6) vapor used to deposit the W and create Aluminum Fluoride (AlF3), which is an alloy with higher resistivity and other undesirable properties.
Referring to FIG. 2, a first metal feature 200 is formed on a first insulating layer 210. The first metal feature 200 is part of a first patterned metal layer having a lower metal layer 202, an intermediate, primary conductive layer 204, such as Al or an Al alloy, and an upper anti-reflective coating 206. A through-hole 220 is etched in a second dielectric layer 230 and 280, having been formed on the first patterned metal layer. The through-hole 220 is etched completely through the anti-reflective coating 206, resulting in a concavity 222 in the primary conductive layer 204. Depending on the etching chemistry employed and the solvents used to clean the etched through-hole 220, a portion of the conductive layer 104 beneath the anti-reflective coating 206 is typically penetrated and undercut as the thickness of the anti-reflective coating 206 is optimized for photolithographic processing. Thus, the concavity 222 can extend beneath non-etched portions of the anti-reflective coating 206.
The adhesion promoting layer 150 is conventionally deposited by physical vapor deposition (PVD) or other sputtering techniques and does not provide an effective barrier to the interaction of Al with WF6 during the W deposition. In particular, sputtering TiN does not provide good coverage of the exposed primary conductive layer 104, especially when the primary conductive layer 104 includes an upper surface with a concave portion undercutting the anti-reflective coating 106.
One conventional remedial technique is to sputter a rather thick adhesion promoting layer 150, e.g. about 700 xc3x85 to about 800 xc3x85, in an attempt to provide an effective diffusion barrier. However, this approach is disadvantageous because the thick adhesion promoting layer may pinch off the via, leading to voids and increased electrical resistance. Moreover, the resistivity of the adhesion promoting layer 150 is higher, resulting in an increased electrical resistance for the via. Furthermore, sputtering TiN results in a crystalline structure which, even at that thickness, is not entirely effective in reducing diffusion and hence the interaction of Al and WF6, since grain boundaries provide a rapid diffusion path.
Variations in the thickness of the second dielectric layer 130 above the first metal feature extend the minimum required time in etching the through-holes in the second dielectric layer 130. If the etch time is too short, then some through-holes do not reach the metal layer, resulting in a failed electrical connection. On the other hand, if the etching time is too long, then some of the through-holes punch through to the Al of the first metal layer, also resulting in poor electrical connections. The acceptable range of etching time is termed a xe2x80x9cprocess window.xe2x80x9d In general, a wider process window is more desirable than a narrower process window, because the wider process windows allows for a greater variety of features, for example, shallow and deep contacts, and larger and smaller contacts. Deep contacts are etched for a longer period of time than shallow contacts, and larger contacts etch faster than smaller contacts.
Accordingly, a conventional approach for widening the process window is to increase the thickness of the anti-reflective coating 106, since the anti-reflective coating 106 etches at a much slower rate than the second dielectric layer 130, for example, ten times slower. Thus, a relatively thick anti-reflective coating 106, generally in the range of about 800 xc3x85 to 1200 xc3x85, but typically about 1000 xc3x85, is conventionally used to achieve an acceptable process window. There are, however, disadvantages caused by such a thick anti-reflective coating 106. For example, anti-reflective coatings 106 have a higher resistivity and hence thicker anti-reflective coatings 106 result in increased electrical resistance. As another example, thick anti-reflective coatings 106 increases the height of the topography, creating problems such as making planarization more difficult.
There exists a need for a high-density multilevel semiconductor device with design features of 0.25 microns and under and a reliable interconnection structure. A need also exists for a method of manufacturing such a semiconductor device.
There is a need for accommodating a greater variety of features in a semiconductor device, e.g. by widening the process window of etching through-holes without increasing the thickness of the anti-reflective coating.
There exists a need for reducing the thickness of the anti-reflective coating while maintaining the same width of the process window.
There is also a need for preventing the interaction of Al and WF6 in the case that etching of through-holes punches through the anti-reflective layer. Specifically, there exists a need for depositing an effective diffusion barrier that avoids pinching off the vias.
These and other needs are met by the present invention, in which the adhesion promoting layer is deposited by a chemical vapor deposition (CVD) technique. The CVD deposited layer has an amorphous structure and can be formed at a reduced thickness, e.g., about 35 xc3x85 to about 250 xc3x85. Advantageously, the CVD deposited adhesion promoting layer prevents pinch off, and, at the same time functions effectively as a diffusion barrier between the Al and the WF6. Consequently, the process window can be widened without the concerns associated with punch through in conventional structure, and/or the thickness of the anti-reflective coating can be reduced, e.g. to about 250 xc3x85 to about 750 xc3x85.
Additional needs, objects, advantages, and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The needs, objects, and advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
Accordingly, one aspect of the present invention is a semiconductor device comprising: a first dielectric layer formed on a substrate; a patterned metal layer having gaps, formed on the first dielectric layer and including a metal feature with an upper surface; a second dielectric layer formed on the patterned metal layer; a through-hole having an internal surface formed in the second dielectric layer exposing a portion of the upper surface of the metal feature, wherein the exposed portion of the upper surface has a concave section formed during etching the through-hole; a layer of chemical vapor deposited barrier metal lining the internal surface of the through-hole and the concave section of the upper surface of the metal feature; and conductive material filling the through-hole and forming a via.
Another aspect of the present is a method of manufacturing a semiconductor device comprising: forming a first dielectric layer on a substrate; forming a patterned metal layer having gaps on the first dielectric layer, wherein the patterned metal layer includes a metal feature with an upper surface; forming a second dielectric layer on the patterned metal layer; etching to form a through-hole having an internal surface in the second dielectric layer, expose a portion of the upper surface of the metal feature, and form a concave portion in the upper surface of the metal feature; and depositing a layer of barrier material by chemical-vapor-deposition to line the internal surface of the through-hole and the concave portion of the metal feature.
Additional needs, objects, and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.